Question: PRELAB PLEASE. Lab #3: Mealy Sequential Circuit 1. Requirement Design a Mealy Sequential Circuit which investigates an input sequence X and which will produce an

PRELAB PLEASE.

PRELAB PLEASE. Lab #3: Mealy Sequential Circuit 1. Requirement Design a Mealy

Lab #3: Mealy Sequential Circuit 1. Requirement Design a Mealy Sequential Circuit which investigates an input sequence X and which will produce an output of Z 1 for any input sequence sequence 001 has occurred at least once. See table below for a sample set of input sequence. A reset signal RST will reset the circuit (reset the circuit to the initial state). ending in 1?10, provided that the Input 1 0 1 0 0 1 0 1 01 0 0 0 1 Mealy Sequential Circuit RST CLK 2. Pre-lab . State graph State table

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