Circuit below represents a given circuit, the circuit has two inputs A and $B$ two bits each and two outputs $S$ three bits and overflow $1$ bit.

If bit $A[1]$ is greater than bit $B[1]$ the circuit shall calculate $A-B$ otherwise, the circuit calculates $A+B.$

Three full adders are used here noticing that the third full adder is used to handle over flow cases only with inputs $0$ for both A and $B.$

Write Verilog structural code for this circuit, you are to instantiate the full adder circuit that you built before for three times, for FA$2$ the ports should be:

FA $($S$[2],$ Cout$[3],0,0,$ Cout$[2])$

Write Verilog testbench code for this circuit, you are to consider all possible values for inputs A and B$,$ you are also to use $monitor instruction