code $1$:library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity D$\_$ff is

port $($

clk : in bit;

d : in bit;

reset : in bit;

qout : out bit

$)$;

end D$\_$ff;

architecture Behavioral of D$\_$ff is

signal q$\_$int : bit :$=\text{'}0\text{'}$;

begin

process $($clk$,$ reset$)$

begin

if reset $=\text{'}0\text{'}$ then

q$\_$int ;

elsif clk'event and clk $=\text{'}1\text{'}$ then

q$\_$int d;

end if;

end process;

Copy

qout q$\_$int;

end Behavioral; code $2$:library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity mux$\_2\_1$ is

Port $($

a : in bit$\_$vector$(1$ downto $0)$;

b : in bit;

c : out bit

$)$;

end mux$\_2\_1$;

architecture Behavioral of mux$\_2\_1$ is

begin

c a$(0)$ when $($b $=\text{'}0\text{'})$ else a$(1)$;

end Behavioral;$\backslash \backslash$ use these two codes as a component to design a top level code fot $8$ bit parallel in and parallel out shift register $.$ the shift register is capable of loading parallel data or shifting data to the right direction $.$ the cicuit has $8-$bits input data and $8-$bit output data $,$ clock $,$ and select input $.$ the parallel loading operation occures when $($select$=\text{'}0\text{'})$ and shifting data to the right direction occurs when select$=\text{'}1\text{'}$