code from last lab

module ALU(A, B, reset, opcode,result );

input [8:0] A, B;

input reset;

input [2:0] opcode;

output reg [16:0]result;

always @(A or B or reset or opcode)

begin

if(reset == 1) begin

result

'b0;

end

else begin

case(opcode)

3'b000 : result

3'b001 : result

3'b010 : result

3'b011 : result

3'b100 : result

3'b101 : result

3'b110 : result

3'b111 : result

endcase

end

end

endmodule

module ALUTb();

reg [8:0] A, B;

reg [2:0] opcode;

reg reset;

reg [2:0]i;

wire [16:0] result;

ALU UUT0(A, B, reset, opcode,result);

Initial

Begin

reset = 1 ;

#10

reset = 0;

for (i=0,i

begin

opcode = i ;

A = 8'b11111111;

B = 8'b00000001;

#10;

end

end

end

endmodule

read an instruction from instruction memory by PC (1): Design an instruction fetcher that the designed accumulator last lab session after each clock cycle value, generated by MEM: PC 7:0 MEMInstruction[31:0) CLK Define a memory by: Reg [31:0] mem_a [255:0]: This is a memory block with 256 memory cells and 32 bits data width for each cell. Access each cell by always@(posedge clk)begin INS mem-a[address] ; nd The above block will read an instruction from memory block by address value and store the instruction into register "INS" read an instruction from instruction memory by PC (1): Design an instruction fetcher that the designed accumulator last lab session after each clock cycle value, generated by MEM: PC 7:0 MEMInstruction[31:0) CLK Define a memory by: Reg [31:0] mem_a [255:0]: This is a memory block with 256 memory cells and 32 bits data width for each cell. Access each cell by always@(posedge clk)begin INS mem-a[address] ; nd The above block will read an instruction from memory block by address value and store the instruction into register "INS