Computer architecture

Question 9)

a) What is the average memory access time in a system with a CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles, cache miss rate = 5%.

b) Given a system with a single level cache, a miss penalty of P cycles, and a hit time of H cycles, how high does the cache miss rate have to be in order for the L1 cache to not be useful (in terms of H and P).