Consider a classical pipelined architecture with the following reservation table:

hardware resources:

instruction memory

register bank read $1$

register bank read $2$

ALU

data memory

register bank write

a$.$ Suppose instruction $\text{'}D\text{'}$ depends on the results of instruction $\text{'}A\text{'}.$ What kind of

pipelining hazard is this? Does this hazard occur in the reservation table above? If yes, at

which clock cycle$($s$)?$

b$.$ Suppose your microcontroller only has one memory port, meaning that reading from

memory and writing to memory cannot be performed at the same time. What kind of

pipelining hazard is this? Does this hazard occur in the reservation table above? If yes, at

which clock cycle$($s$)?$

c$.$ Suppose instruction $\text{'}$A$\text{'}$ is a conditional branch instruction. What kind of pipelining

hazard is this? Does this hazard occur in the reservation table above? If yes, at which clock

cycles?