Consider a direct$-$mapped cache for a MIPS processor with the following characteristics: $1.$ The total cache size $($without counting the bits for valid bits and tags$)$ is $256$MB$(228$ bytes$)$; $2.$ The cache block size is eight words $(4$ bytes$/$word$)$; $3.$ The address is $32$ bits; Questions: $1.$ How many blocks can the cache hold? $2.$ What is the size of the tag field? $3.$ When accessing the memory address with a hex format of OxFFFF$82$AO$,($a$).$ Which cache block will this address be mapped to $?$ hex format$)($b$).$ What is the value of the tag field? $($in hex format$)$