Consider a pipeline with forwarding, hazard detection, and 1 cycle delay for branch taken. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the following MIPS instruction sequence, draw a pipeline diagram (i.e. graphical representation). List all data stalls (use bubble or X). Mark all data forwards. What is the final execution time (# of cycles) of the code?

LW R2, 0(R2)

BEQ R2, R1, L //assume branch not taken

AND R9, R2, R1

OR R4, R9, R2

L: AND R5, R4, R9