Consider a processor datapath architecture that includes components with the following latencies

Memory access: 200 ps

ALU and addition operations: 150 ps

Register file access (read or write): 100 ps

Assume routing elements and control units have no delay.

For an instruction mix composed of 20% loads, 15% stores, 45% ALU ops, 15% branches, 5% jumps compare the single fixed clock cycle and multiple clock cycle per instruction approaches, i.e.

a) what is the nominal clock period per instruction and CPI for the fixed cycle approach?

b) what is the nominal clock period and CPI for the multiple cycle approach? Assume buffers introduced between stages (e.g. IR, A, B, ALUout etc.) add an extra 20ps delay per stage in the multicycle case.

c) what is the ratio of the execution times assuming the same program (with the given instruction mix) is run on both processors?