Consider a processor in which the only instructions that read data from or write data to memory are loads $(15\%$ of all instructions$)$ and stores $(10\%$ of all instructions$),$ respectively.

There are three levels of cache $($L$1,$ L$2,$ and L$3),$ followed by main memory. The L$1$ contains a split cache, while L$2$ and L$3$ are unified caches. The L$2$ cache is an inclusive cache $($it is a superset of L$1$ caches$),$ but the L$3$ cache follows a non$-$inclusive, non$-$exclusive policy $($i$.$e$.,$ a block in L$2$ may or may not exist in L$3).$ We assume all blocks exist in main memory. There is no structural hazard due to number of ports.