Consider a two-level cache. In 1000 memory references, there are 50 misses in the first level and 10 misses in the second level. What are the local rate for L1 and L2? What is the global miss rate? Assume the hit time of L1 is 1 cycle, the hit time of the L2 cache is 10 clock cycles, the miss penalty from the L2 cache to memory is 500 cycles, and there are 1.3 memory references per instruction. No need to consider write operations in this problem. What is the average memory access time? What is the average stall cycles per instruction?