Question: Consider following loop: Loop: LW r2, 0(r2) BEQ r2, r0, LOOP OR r2, r2, r3 SW r2, 0(r5) Assume that there is no delay slot

Consider following loop:

Loop: LW r2, 0(r2) BEQ r2, r0, LOOP OR r2, r2, r3 SW r2, 0(r5)

Assume that there is no delay slot and the next PC located in ID stage. Also, assume that the loop is iterated for 100 times.

a) Draw the pipeline diagram for the first 2 iterations

b) How many cycles does it take to complete the instruction sequence?

c) If a one-bit branch predictor is used, which is initialized to N(i.e. branch not taken), how many correct and wrong predictions that it will produce?

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