Consider the final MIPS single cycle implementation below.

Assume that each of the logic block used in the processor's datapath has the following latencies.

"Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File.

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Assuming these values, answer the following questions. Write your explanations for obtaining each answer. For each question, indicate the critical path.

a$.$What is the latency of an R$-$type instruction $($i$.$e$.,$ how long must the clock period be to ensure that this instruction works correctly$)?$

b$.$What is the latency of lw$?$

c$.$ What is the latency of sw$?$

d$.$What is the latency of beq?

e$.$What is the latency of an arithmetic, logical$,$ or shift I$-$type $($non$-$load$)$ instruction?

f$.$What is the minimum clock period for this CPU?