Question: Consider the following 3 2 - bit MIPS single cycle datapath designed for R - type ( add , sub, and, or , slt )

Consider the following 32-bit MIPS single cycle datapath designed for R-type (add, sub, and, or, slt),
sw, Iw and beq instructions
The values of control signals needed to execute beq instruction are:
a. PCLoad=1, RegWrite=0, ALUSrc =0, RegDst =1, Branch =0, MemRead =0, MemWrite =0, MemtoReg =x
b. None of these
c. PCLoad =1, RegWrite =0, ALUSrc =0, RegDst =x, Branch =1, MemRead =0, MemWrite =0, MemtoReg =x
d. PCLoad=1, RegWrite=1, ALUSrc=1, RegDst=X, Branch=0, MemRead=0, MemWrite=1, MemtoReg=X
e. PCLoad=1, RegWrite =0, ALUSrc =1, RegDst =x, Branch =1, MemRead =0, MemWrite =0, MemtoReg =x
Consider the following 32-bit MIPS single cycle datapath designed for R-type

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