Consider the following behavior of a sequential logic. A state machine for this behavior will have one input named X, one output named Z, and a 2-bit register (using D-type flip-flops) for state information. Assume that the state is represented by the Q₁Q₀ signals of the register.

The four states are coded as: Q₁Q₀ = 00 means S₀; Q₁Q₀ = 01 means S₁; Q₁Q₀ = 10 means S₂; and Q₁Q₀ = 11 means S₃.

I. Begin by completing a state transition table based on the state diagram shown above.

II. Realize the next state logic and the output logic of this state machine using a minimum amount of traditional gates (ANDs, ORs, and NOTs). Draw and test the complete circuit in Logisim, clearly label all inputs and outputs, and attach your completed work as a Logisim circuit file.

III. Realize the next state logic and the output logic of this state machine using 4:1 multiplexers and other gates. Use the state variables Q₁Q₀ as the multiplexer selects. Draw and test the complete circuit in Logisim, clearly label all inputs and outputs, and attach your completed work as a Logisim circuit file.

IV. Realize the next state logic and the output logic of this state machine using a ROM. Include the binary contents of all ROM locations. Draw and test the complete circuit in Logisim, clearly label all inputs and outputs, and attach your completed work as a Logisim circuit file.