Consider the following behavior of a sequential logic. A state machine for this behavior will have one input named $x,$ one output

named $Z,$ and a $2-$bit register $($using D$-$type flip$-$flops$)$ for state information. Assume that the state is represented by the $Q_1{Q}_0$ signals

of the register. The four states are coded as follows: $Q_1{Q}_0=00$ means $S_0$;$Q_1{Q}_0=01$ means $S_1$;$Q_1{Q}_0=10$ means $S_2$; and $Q_1{Q}_0=$

$11$ means $S_3.$

$($Recall that your next$-$state logic must generate the control signals which will cause the next state value to be stored in the register! Since we

are using a D$-$type flip$-$flop in this assignment, the D$1$ and D$0$ control signals shown in the diagram are the same as the Q$1+$ and Q$0+$ next$-$

state values, so we will simply refer to them as Q$1+$ and Q$0+$ to avoid confusion. Keep in mind, however, that J$-$K flip$-$flops, T flip$-$flops, or

other devices may require different control signals.$)$ II$.(10$ points$)$ In the $"$Q$2"$ subcircuit, realize the next state logic and the output logic of this state machine using $4$:$1$ multiplexers and

other gates as needed. Use the state variables Q$\_(1)$Q$\_(0)$ as the multiplexer selects.