Consider the following VHDL code and identify the syntax error$($s$)$ within it:Select one:a$.$ The selected signal assignment syntax is incorrect for VHDL$.$b$.$ The SEL signal's range is too large for the provided selection cases.c$.$ The concatenation operation $\text{'}0\text{'}$ & IN$\_$A & IN$\_$B generates a BIT$\_$VECTOR of incorrect size for OUTPUT.d$.$ The literal $\text{'}0\text{'}$ is of type BIT, which cannot be concatenated with BIT$\_$VECTOR types without explicit conversion.