Consider the sequential circuit implementing a serial adder built of a 1-bit full adder and a D flip-flop and

1. Create the state table and the state diagram of the circuit.

2. Implement the serial adder circuit as a module in Verilog. Use only gate-level modeling.

3. Create a test module that uses the serial adder module to add 16-bit two's complement integers. Run it with at least 8 test sequences that add:

the largest integer to itself

the largest integer to 1

the largest integer to 0

the largest integer to -1

the smallest integer to 1

the smallest integer to 0

the smallest integer to -1

the smallest integer to the largest integer