Question: Consider the SystemVerilog module below. module foo ( input logic [ 3 : 0 ] aa , output logic bb ) ; assign bb =

Consider the SystemVerilog module below.
module foo(input logic [3:0] aa, output logic bb); assign bb =^{15{aa[3:1]}}; endmodule
Assuming the module functions as intended, which of the following hexadecimal test vectors will validate it, in which the bits are interpreted as {aa,bb,bb,bb,bb}?
Question 15Answer
a.
50
b.
40
c.
7F
d.
70
e.
F0

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