Consider this MIPS code segment.

loop:

sub $$t3,$$$t3,$$$to$

add $to$,$ $to$,$ $to

addi $$t1,$$$t0,5$

hw $t$2,$ O$($$to$)$

add $$t2,$$$t2,1$

sw $5+2,0(5t1)$

bgt $t$3,$ $eero, loop

outside

Show the timing of this instruction sequence for a $5-$stage pipeline to execute up to the start of one iteration of the loop with forwarding. Use an S where a stal is required to resolve a hazard. Assume that data can be written to registers and read from registers in the same cycle and that the processcr's only rectiving end of the forwarding logic is just after we read registers in the decode stage llate in the second half of the cycle$)$

Download pipeline chart:

PDF Version darr

Wand Version &t

Upload your completed pipeline.

$\backslash$table$[[$eyc$,1.,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,$AB$,19,24],[$sub$,$F$,0,$E$,$M$,w,,,,,,,,,,,,,,,],[$ads$,,,,,,,,,,,,,,,,,,,,],[$add$,,,,,,,,,,,,,,,,,,,,],[$Iw$,,,,,,,,,,,,,,,,,,,,],[$add$,,,,,,,,,,,,,,,,,,,,],[sw,,,,,,,,,,,,,,,,,,,,],[$ber$,,,,,,,,,,,,,,,,,,,,],[$eutidet$,,,,,,,,,,,,,,,,,,,,],[y.b,,,,,,,,,,,,,,,,,,,,]]$