Consider this MIPS code segment.

loop:

sub $t$3,$ $t$3,$ $t$0$

add $t$0,$ $t$0,$ $t$0$

addi $t$1,$ $t$0,5$

lw $t$2,0($$t$0)$

add $t$2,$ $t$2,1$

sw $t$2,0($$t$1)$

bgt $t$3,$ $zero, loop

outside

Show the timing of this instruction sequence for a $5-$stage pipeline to execute up to the start of one iteration of the loop with forwarding. Use an S where a stall is required to resolve a hazard. Assume that data can be written to registers and read from registers in the same cycle and that the processor's only receiving end of the forwarding logic is just after we read registers in the decode stage $($late in the second half of the cycle$)$