Copy and pasteable code: module alu( input [3:0] A,B, // ALU 4-bit Inputs input [3:0] ALU_Sel ,// ALU Selection output [3:0] ALU_Out , // ALU 4-bit Output output CarryOut // Carry Out Flag ); reg [7:0] ALU_Result; wire [4:0] tmp; assign ALU_Out = ALU_Result; // ALU out assign tmp = {1b0 ,A} + {1b0 ,B}; assign CarryOut = tmp [4]; // Carryout flag always @(*) begin case(ALU_Sel) 4b0000: // Addition ALU_Result = A + B; 4b0001: // Subtraction ALU_Result = A - B; 4b0010: // Multiplication ALU_Result = A ** B; 4b0011: // Division ALU_Result = A/B; 4b0100: // Logical shift left ALU_Result = A>1; 4b0110: // Rotate left ALU_Result = {A[2:0] ,A[3]}; 4b0111: // Rotate right ALU_Result = {A[3],A[3:1]}; 4b1000: // Logical and ALU_Result = A && B; 4b1001: // Logical or ALU_Result = A || B; 4b1010: // Bitwise xor ALU_Result = A ^ B; 4b1011: // Logical nor ALU_Result = A || B ); 4 b1100 : // Logical nand ALU_Result = A && B ); 4 b1101 : // Bitwise xnor ALU_Result = A ^ B ); 4 b1110 : // Greater comparison ALU_Result = (A >B) ? 4 b0 : 4 b1 ; 4 b1111 : // Equal comparison ALU_Result = (A==B) ? 4b1 : 4b0; default: ALU_Result = A + B; endcase end endmodule

1. Create the testbench, called tb alu.v and add it to your Vivado project. You can use the testbench from lab 0 as a starting point. 2. Test the Addition (0000) operation. (a) Modify the testbench to provide stimulus that sets ALU sel to the appropriate op code and sweeps through all possible combinations of inputs from A=0000, B=0000 to A=1111, B=1111. Include the simulation waveform in your report. (Note: only report several com- binations of A and B. Explain the different parts of these waveform in details such as, the inputs, the outputs, and the expected result.)

(b) Is the operation implemented correctly? If not, indicate on the waveform where at least one of outputs was incorrect. Identify which line in alu.v contains the mistake, and propose a correction to this line in you report. Create a new file called alu fixed.v with the mistakes being corrected. The ports declaration should be the same as alu.v and the name of the new module should be alu fixed. Any changes in the port declaration will cause your module to fail during grading and you will lose all the points. 3. Repeat Step 2(a-b) for the following operations: multiplication, logical shift left, rotate right, logical AND, and greater comparison. Note: If the operation is not implemented correctly, you need to report the simulation waveform for at least one of the parts for which the output was incorrect. If the operation is implemented correctly, you need to report the simulation waveform for only 2-3 parts of the waveform and show why the outputs are correct. Note: Remember the fixed version of your ALU has to fix all the bugs. For example, the carryout is not implemented correctly in the given ALU. You need to think how to fix it to make sure that your operations are running correctly. Note: Your module name of the the fixed version of the alu has to be called (alu fixed) with the same ports names as the provide module above. The file name has to be called (alu fixed.v)

Code from lab 0:

module HA ( A, B, Sum , Carry ); input A; input B; output Sum; output Carry; assign Sum = A ^ B; // bitwise xor assign Carry = A & B; // bitwise and endmodule // half_adder

Testbench from lab 0: module tb_HA; reg r_A = 0; reg r_B = 0; wire w_Sum; wire w_Carry; HA HA_inst ( .A(r_A), .B(r_B), .Sum(w_Sum), .Carry(w_Carry) ); initial begin r_A = 1b0; r_B = 1b0; #10; r_A = 1b0; r_B = 1b1; #10; r_A = 1b1; r_B = 1b0; #10; r_A = 1b1; r_B = 1b1; #10; end endmodule // tb_HA

Below you see the Verilog code for the ALU. Create a new Vivado project and copy this code to a file named alu.v. Code 1: 4-bit ALU. module alu input [3:0] A,B, // ALU 4-bit Inputs input [3:0] ALU_Sel,// ALU Selection output [3:0] ALU_Out, // ALU 4-bit Output output CarryOut // Carry Out Flag ); reg [7:0] ALU_Result; wire [4:0] tmp; assign ALU_Out = ALU_Result;// ALU out assign tmp = {1'50, A} + {1'50,B}; assign CarryOut = tmp [4]; // Carryout flag always (*) begin case (ALU_Sel) 4'50000; // Addition ALU_Result = A + B; 4' 50001: // Subtraction ALU Result = A - B; 4'50010: // Multiplication ALU_Result = A ** B; 4' 0011: // Division ALU Result = A/B; 4' 0100: // Logical shift left ALU Result = A>1; 4'50110: // Rotate left ALU_Result = {A (2:0), A[3] }; 4' 0111: // Rotate right ALU_Result = {A [3] , A (3:1] }; 4'b1000: // Logical and ALU_Result = A && B; 4' 51001: // Logical or ALU_Result = A || B; 4' 61010: // Bitwise xor ALU_Result = A^ B; 4'b1011: Logical nor ALU Result = A 11 B); 4'b1100: // Logical nand ALU_Result = A & & B); 4'b1101: // Bitwise xnor ALU_Result = A - B); 4'b1110: // Greater comparison ALU Result - (AB) ? 4'bo : 4'61; 4'b1111: // Equal comparison ALU_Result = (A==B) ? 4'bi : 4'60; default: ALU_Result = A + B; endcase end endmodule