Could you expline in words this VHDL code(FIR Filter Design ) ???????????

library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_std.all;

use STD.TEXTIO.all;

entity fir_mid is port ( clk : in std_logic; rst : in std_logic; i_valid : in std_logic; in_filter: in signed (15 downto 0); o_valid : out std_logic; out_fir : out signed (15 downto 0) ); end fir_mid;

architecture RTL of fir_mid is

-- dealy type shift_reg is array(36 downto 0) of signed (15 downto 0); signal reg_shift :shift_reg;

--change to 17 bit,sign extention type shift_reg1 is array (36 downto 0) of signed (16 downto 0); signal reg_shift1 :shift_reg1;

-- Add type Sum is array (18 downto 0) of signed (16 downto 0); signal Addition :Sum;

--Multiplication type Mult is array (18 downto 0) of signed (32 downto 0); signal Multip :Mult; type Mult1 is array (18 downto 0) of signed (19 downto 0); signal Multip1 :Mult1;

signal f_valid :std_logic_vector(10 downto 0):= (others => '0');

type t_sum is array (18 downto 0) of signed (16 downto 0); signal sum0 : t_sum:=(others=> (others=>'0'));

signal mul12 : Mult1:=(others => (others=>'0')); signal mul15 : Mult1:=(others => (others=>'0')); signal sum1 : signed (19 downto 0):= (others=>'0');

type coefficients is array (0 to 18)of integer; signal TAPS :coefficients :=(146, 283, 439, 501, 345, -134, -966, -2041, -3081, -3661, -3293, -1549, 1788, 6610, 12440, 18482, 23773, 27393, 28680); begin --STEP 1,2,&3 Ss:process(clk,rst)

begin -- dealy if (rst='1')then reg_shift <= (others =>(others =>'0')); elsif(clk'event and clk='1')then if (i_valid = '1') then reg_shift <= reg_shift (35 downto 0) & in_filter; end if; end if; end process; ------------------ --change to 17 bit,sign extention M1:process(clk,rst)

begin -- sign ext if (rst='1')then reg_shift1 <= (others =>(others =>'0')); elsif(clk'event and clk='1')then

for i in 0 to 36 loop reg_shift1(i) <= reg_shift(i)(15)& reg_shift(i); end loop; end if; end process M1;

SR1:process(clk,rst)

begin -- Add if (rst='1')then Addition <= (others =>(others =>'0')); elsif(clk'event and clk='1')then

for i in 0 to 18 loop Addition(i) <= reg_shift1(i)+ reg_shift1 (36-i); end loop; Addition(18) <= reg_shift1(18);

end if; end process ;

SR:process(clk,rst)

begin -- Multiplication if (rst='1')then Multip <= (others =>(others =>'0')); elsif(clk'event and clk='1')then for i in 0 to 18 loop Multip(i)<= Addition(i)* to_signed (TAPS(i),16); end loop; end if; end process;

process(clk,rst) begin if (rst='1')then mul15 <= (others =>(others =>'0')); elsif(clk'event and clk='1')then for i in 0 to 18 loop mul15(i)<= Multip(i)(32) & Multip(i)(32 downto 14);

end loop; end if; end process;

SR2:process(clk,rst)

begin -- Addition if (rst='1')then sum1 <= (others =>'0'); elsif(clk'event and clk='1')then sum1<=mul15(0)+mul15(1)+mul15(2)+mul15(3)+mul15(4)+mul15(5)+ mul15(6)+mul15(7)+ mul15(8)+mul15(9)+mul15(10)+mul15(11)+ mul15(12)+mul15(13)+mul15(14)+mul15(15)+mul15(16)+mul15(17)+mul15(18);

end if; end process; process(clk) begin if(clk'event and clk='1')then f_valid(0)<=i_valid;

for i in 0 to 9 loop f_valid(i + 1)<=f_valid(i); end loop; end if; end process;

o_valid<=f_valid(9); out_fir<=sum1(18 downto 3);

end RTL;