Create and add the VHDL module with two $2-$bit inputs $($x$0,$ x$1,$ y$0,$ y$1),$ a one bit select input $($s$),$ and two$-$bit output $($m$0,$ m$1)$ using structural modeling.

A two$-$bit wide multiplexer will have input busses x$[1$:$0]$ and output bus y$[1$:$0].$ Thus, you will need to instantiate four $(4)$ AND$2$ gates and two $(2)$ OR$2$ gates, as well as one $(1)$ INV gate.

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