Create testbench code to test multuple values in SystemVerilog for this OTTER Register file, this is my code that only tests one set of values:

module tb$\_$REGFILE;

reg $[4$:$0]$ ADR$1$;

reg $[4$:$0]$ ADR$2$;

reg $[4$:$0]$ WADR;

reg $[31$:$0]$ WDATA;

reg WE;

reg clk;

logic $[31$:$0]$ RS$1$;

logic $[31$:$0]$ RS$2$;

REGFILE UUT $($

$.$ADR$1($ADR$1),$

$.$ADR$2($ADR$2),$

$.$WADR$($WADR$),$

$.$WDATA$($WDATA$),$

$.$WE$($WE$),$

$.$clk$($clk$),$

$.$RS$1($RS$1),$

$.$RS$2($RS$2)$

$)$;

initial begin

clk $=0$;

forever #$10$ clk $=$ ~clk;

end

initial begin

ADR$1=5\text{'}$b$00000$;

ADR$2=5\text{'}$b$00001$;

WADR $=5\text{'}$b$00010$;

WDATA $=32\text{'}$h$00000000$;

WE $=1\text{'}$b$0$;

#$10$;

WDATA $=32\text{'}$h$12345678$;

WE $=1\text{'}$b$1$;

#$10$;

WE $=1\text{'}$b$0$;

#$10$;

$finish;

end

endmodule