$($d$)$ Write a Verilog description of the system.

$4\mathrm{.}11$ An $nn$ array multiplier, as in Figure $4-29,$ takes $3n-4$ adder delays $+1$ gate delay to calculate a product. Design an array multiplier that is faster than this for $n>4.($Hint: Instead of passing carry output to the left adder, pass it to the diagonally lower one, speeding up the critical path. This topology is called "multiplier using carry$-$save adder."$)$