DATAPATH:

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When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In a single cycle datapath where Instruction Memory (I-mem), Add, Mux, ALU, Regs, Data Memory (D-mem), and control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. Branch Add Add M U ALU operation Data PC Address Instruction Register # Registers Register # M MemWrite ALU - Address Data memory Zero Instruction memory 3X | Register # RegWrite Data MemRead Control What is the clock cycle time without this improvement? You can consult the image for reference. 1430 * Answer: 1130