$4\mathrm{.}10$ When processor designers consider a possible improvement to the

processor datapath, the decision usually depends on the

cost$/$performance trade$-$off. In the following three problems, assume

that we are beginning with the datapath from Figure $4\mathrm{.}21,$ the latencies

from Exercise $4\mathrm{.}7,$ and the following costs:

IMem

Register

File

Mux ALU Adder

DMem

Single

Register

Sign

extend

Sign

gate

Control

$10002001010030200051001500$

Suppose doubling the number of general purpose registers from $32$ to

$64$ would reduce the number of lw and sw instruction executed by $12\%,$

but increase the latency of the register file from $150$ ps to $160$ ps and

double the cost from $200$ to $400.($Use the instruction mix from Exercise

$4\mathrm{.}8$ and ignore the other effects on the ISA discussed in Exercise $2\mathrm{.}18.)$

$4\mathrm{.}10\mathrm{.}1[5]<4\mathrm{.}4>$ What is the speedup achieved by adding this

improvement?

$4\mathrm{.}10\mathrm{.}2[10]<4\mathrm{.}4>$ Compare the change in performance to the

change in cost$.$

$4\mathrm{.}10\mathrm{.}3[10]<4\mathrm{.}4>$ Given the cost$/$performance ratios you just

calculated, describe a situation where it makes sense to add more

registers and describe a