Design a $3-$bit parallel load shift register using four T flip$-$flops $($labeled T$1,$ T$2,$ and T$3)$ and a LOAD

input. This register should allow loading of parallel data through inputs M$1,$ M$2,$ and M$3$ when

LOAD is active, and shift the data to the right on each clock pulse when LOAD is inactive.

a$)$ Create the State Diagram: Show the states of the four flip$-$flops $($Q outputs$)$ when shifting data

to the right, including the initial loading of M$1,$ M$2,$ and M$3$

b$)$ Complete the State Table: Using the excitation table for T flip$-$flops, fill out the state table

indicating the transitions of each flip$-$flop based on LOAD and the clock signa