Design a 4-bit Up-Down counter. An UpDown signal is available that determines the type of counter (Ascending or Descending), the counter will be limited by the value of the 4-bit signal called Pset and we also have a 2-bit signal called Frec which sets the speed of the counter. When the signal reset (RST) is set to 1, the output value must be equal to the PSet value, the CLK signal corresponds to the the 12MHz frequency. The signals they should use are summarized in the following table.

a) When the account is ascending it will follow the following sequence: 0 to PSet b) When the account is descending, it will count in this way: PSet to 0

All the program must be done in Xilins VHDL 

Signal CLK Value X 0 RST 1 0 1 UpDown Pset Function Corresponds to the 12 Mhz clock signal Take no action Set the value of the output to the value of Pset Count ascending Countdown 4-bit number used to set the output whe the rst signal is equal to 1, also defines the maximum number of the counter Counting time of 0.5 seg Counting time of 1 seg Counting time of 3 seg Counting time of 5 seg X 0 1 2 Frec 3 Cont_Up Down CLK RST Dout UpDown PSet Frec Signal CLK Value X 0 RST 1 0 1 UpDown Pset Function Corresponds to the 12 Mhz clock signal Take no action Set the value of the output to the value of Pset Count ascending Countdown 4-bit number used to set the output whe the rst signal is equal to 1, also defines the maximum number of the counter Counting time of 0.5 seg Counting time of 1 seg Counting time of 3 seg Counting time of 5 seg X 0 1 2 Frec 3 Cont_Up Down CLK RST Dout UpDown PSet Frec