Design a D flip-flop that is asynchronously resettable with a reset input (R) and that also has an enable input (E). Modify a regular D flip-flop (including possibly lower-level views of the flip-flop) and additional combinational logic (i.e., gates, multiplexers, etc.) to design your circuit. Sketch the circuit.

Reminders about enable and set inputs:

• When R = 1, the flip-flop should reset (i.e., state bit stored = 0 or, in other words,
Q = 0) immediately.
• When R = 0, the flip-flop acts like a regular D flip-flop that also responds to the enable input E.
• When E = 1, the D flip-flop should act like a regular D flip-flop: i.e., D passes to Q at each clock edge.
• When E = 0, the D flip-flop should retain its value: i.e., Q = Oprev, regardless of any clock edges.

The reset input has precedence over the enable input: that is, if R = 1, Q = 0, regardless of the value of the E input.