Question: Design a four - bit shift register with a parallel load, using D flip - flops. There are two control inputs: shift and load. When

Design a four-bit shift register with a parallel load, using D flip-flops. There are two control inputs: shift and load. When shift =1, the contents of the register are shifted by one position. New data are transferred into the register when load =1 and shift =0. If both control inputs are equal to 0, the contents of the register do not change. Write theVHDL code also.

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