$(10$marks$)$ Design a four$-$bit shift register with a parallel load, using D flip$-$flops. There are two

control inputs: shift and load. When shift $=1,$ the contents of the register are shifted by one

position. New data are transferred into the register when load $=1$ and shift $=0.$ If both control inputs

are equal to $0,$ the contents of the register do not change. Write the VHDL code also.

Please Draw the logic diagram of a $4-$bit register with four D flip$-$flops and $4$x$1$ multiplexers with mode selection inputs s$1$ and s$0,$ and write the VHDL code also.