a) Design a 4-bit shift register with a parallel load from D flip-flops, AND, OR and NOT gates. The register has two control inputs: shift and load. When shift=1, the contents of the register are shifted right by one position. New data are transferred into the register when load=1 and shift=0. If both control inputs are equal to 0, the content of the register does not change.

b) Write a behavioral Verilog implementation for your register design.