Question: Design a synchronous counter for the sequence: 0,1,3,4,6,7,0,1,3, ..., and consider all the states which will not be appeared as don't care state. Provide

Design a synchronous counter for the sequence: 0,1,3,4,6,7,0,1,3, . . ., and consider all the states which

Design a synchronous counter for the sequence: 0,1,3,4,6,7,0,1,3, ..., and consider all the states which will not be appeared as don't care state. Provide the following: (a) The number of bits required for the counter (b) State diagram (c) State transition table (d) K-Map simplifications for J-K Flip-Flops (e) The circuit diagram

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