Design, and functionally verify a 8x4 (8-deep, 4-bit wide) FIFO queue with the top-level schematics and function table given below (rename the signal R/W as WNR).

In particular, test the state of the FIFO flags for all possible cases (empty, partially empty or partially full, full) as you fill up and empty out the FIFO.

Rrw n 13:01 Full FIFO CLK Empty RST Out 13:0] FIFO Control R'WW EN FIFO Operation nop read write Rrw n 13:01 Full FIFO CLK Empty RST Out 13:0] FIFO Control R'WW EN FIFO Operation nop read write