Question: Design and implement a Verilog module for a BCD counter. The Verilog module below is a starting point. It uses the internal 50 MHz clock,
Design and implement a Verilog module for a BCD counter. The Verilog module below is a starting point. It uses the internal 50 MHz clock, CLOCK_50, to increment a counter, count, every 0.671 seconds. The rightmost (least significant eight bits of count are displayed by green LED outputs, to facilitate testing with simulations. The input pushbutton KEY[0] resets the counter to zero when it goes from not pressed, KEY[0] = 1, to pressed, KEY[0] = 0.
The BCD counting must have three decimal digits, with each counting 0 to 9. This counting is done with three signals, bcd2, bcd1 and bcd0, representing the respective 100-, 10- and 1-second columns on the HEX2, HEX1 and HEX0 displays. The three signals are 4-bit representations of hexadecimal numbers. Ask yourself why hexadecimal numbers are appropriate for counting here and why this necessitates a 4-bit representation.
Complete the module and ? below to have it use a 25-bit count, with the bcd2, bcd1, and bcd0 signals, and represent these signals as respective 100-, 10-, and 1-second columns on the HEX2, HEX1 and HEX0 displays. Admittedly, there is a serious problem with the accuracy of this counting, in that the size of our 25-bit count variable leads to 67.1-, 6.71- and 0.671-second columns.
// A 4-digit BCD counter with HEX2, HEX1 and HEX0 displaying decimal counting digits with (very rough) approximations to decimal digits in the 100, 10 and 1
module I (CLOCK_50, KEY, HEX3, HEX2, HEX1, HEX0, LEDG);
input CLOCK_50;
input [3:0] KEY;
output [0:6] HEX3, HEX2, HEX1, HEX0;
output reg [7:0] LEDG;
reg [24:0] count;
reg [3:0] bcd0, bcd1, bcd2;
always @(posedge CLOCK_50)
begin
second columns.
LEDG <= count[7:0];
count <= count + 1'b1;
end
always @(posedge CLOCK_50)
if (KEY[0] == 0)
begin
bcd0 <= 4'h0;
bcd1 <= 4'h0;
bcd2 <= 4'h0;
end
else if (count == 0)
begin
if (bcd0 == 4'h9)
begin
bcd0 <= 4'h0;
if (bcd1 == 4'h9)
begin
bcd1 <= 4'h0;
?
:
?
end
else
begin
bcd0 <= bcd0 + 1'b1;
end
end
bcd7seg digit3 (4'hF, HEX3); // HEX3 displays a blank value.
bcd7seg digit2 (bcd2, HEX2); // HEX2 displays the value of bcd2.
bcd7seg digit1 (bcd1, HEX1); // HEX1 displays the value of bcd1.
bcd7seg digit0 (bcd0, HEX0); // HEX0 displays the value of bcd0.
endmodule
// The module bcd7seg displays the bcd value on the specified 7-segment display.
module bcd7seg (bcd, display);
input [3:0] bcd;
output [0:6] display;
reg [0:6] display;
always @ (bcd)
case (bcd)
4'h0: display = 7'b0000001;
4'h1: display = 7'b1001111;
4'h2: display = 7'b0010010;
4'h3: display = 7'b0000110;
4'h4: display = 7'b1001100;
4'h5: display = 7'b0100100;
4'h6: display = 7'b1100000;
4'h7: display = 7'b0001111;
4'h8: display = 7'b0000000;
4'h9: display = 7'b0001100;
default: display = 7'b1111111;
endcase
endmodule
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