Directory-Based Cache Coherence (50 points)

Consider the same sequence of memory accesses as above. Assume that 4 processors are connected with a point-to-point interconnect and implement distributed shared memory with a directory-based cache coherence protocol. For the above sequence of instructions, what are the total number of interconnect message transfers while implementing a write invalidate protocol? For each instruction, list the messages that must be sent on the network and the state of the line in the caches and in the directory. Assume that a message can include some control information as well as an address and cache line. Also assume that the home nodes for memory locations X and Y are both associated with processor P4. Assume that X and Y are not in any of the caches at the start of the sequence, the caches are direct-mapped, each cache line only stores one word, and words X and Y map to the same cache line in each cache (X and Y cannot co-exist in a cache at any time).