For a direct$-$mapped cache design with a $32-$bit address, the following bits of the address are used to access the cache. How many data bits are there in the whole cache? Consider $16-$bit for each word.

$\backslash$table$[[$Tag$,$Index,Offset$],[31,30,29,28,27,26,25,24,23,22,21,20,1s,1,\backslash$table$[[8,1]],\backslash$table$[[7,1]],\backslash$table$[[6,1]],15,\backslash$table$[[14,1]],13,12,11,10,9,8,7,6,5,4]]$

The cache line size contains $($ Tag part, Data part, valid bit$)$

$$ A$.$ None of them

B$.1502^8$

C$.1482^{12}$

D$.1282^8$

E$.1492^8$