For a direct$-$mapped data cache design with a $64-$bit address $($with byte

addressing$),$ the following bits of the address are used to access the cache $($stored

data is one word format$).$

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$63-1413-54-0$

a$)$ What is the cache block size $($in words$)?(2$ points$)$

b$)$ How many blocks does the cache have? $(2$ points$)$

c$)$ How many bits in total are required for such a cache implementation? What

is the ratio of total bits required to the data storage bits? $(4$ points$)$