For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: 4. Tag 31-10 Index 9-5 Offset 4-0 a. What is the cache block size (in words)? b. How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? C. Starting from power on, the following byte-addressed cache references are recorded: 0,4,16, 132, 232,160, 1024, 30, 140, 3100, 180, 2180 d. How many blocks are replaced