For the $2-$way set associative $($direct mapped$)$ data cache with $64$ cache sets, $2$ words $(8$ bytes$)$ per block, and LRU cache replacement policy, simulate the data cache with the provided memory reference trace. $[30$ points$]$

$\backslash$table$[[\frac{R}{W},\backslash$table$[[$Memory$],[$Address$]],$Tag,Index,Offset,Result,Memref,$\backslash$table$[[$Update$],[$cache$]]],[R,04D4,,,,,,],[R,011E4,,,,,,],[R,0212C,,,,,,],[R,04D0,,,,,,],[R,011E0,,,,,,],[R,02128,,,,,,],[R,04D4,,,,,,]]$