For the pipelined implementation below, what is the minimum clock cycle time required for each

stage, namely:

a$)$ Data fetch stage

b$)$ Data decode stage

c$)$ Register read stage

d$)$ ALU operation stage

e$)$ Memory read$/$write stage

f$)$ Register writeback stage

What's the max clock speed for this pipelined implementation?

If you could reduce the delay for one component, which would you choose? How much would you

reduce the delay? $($hint: at some point, reducing the delay in one component doesn't help reduce the

clock period$)$

If you could speed up two componenets, which two? How much would you reduce their delays? LC$3$ Pipelined Implementation