For the single$-$cycle datapath in Figure$1,$ all flip$-$flops are written on the clock rising edge, and the delay of each unit is listed as follow : $\{($memory:$200$ps$),($ALU and adder:$100$ps$),($Register file: read $=50$ps$),($Register file: setup $=40$ps$),($MUX:$10$PS$),($Control unit & ALU control unit:$20$ps$)\}.$Calculate the execution time of the add, beq, and lw instructions, respectively $($ignore the delay of the

decoder and generating the control signals$),$ also, which units can tolerate more latency $($i$.$e$.,$ these units are not on the critical path$)?$ What is the maximum frequency that the processor can run at$?$