Question: Given the Logic Function: Y= (A AND B) OR C (a) Implement this function at the gate level (AND gates, OR gates) (b) If AND

Given the Logic Function: Y= (A AND B) OR C

(a) Implement this function at the gate level (AND gates, OR gates)

(b) If AND gates have a delay of 2.5ns, OR gates have a delay of 3ns, and Inverters have a delay of 1ns, what is the total delay of your circuit?

(c) Implement your gate level circuit from (a) in CMOS

(d) Generate a truth table for your function (rows of table must be in numerical order)

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