How do I solve this error:

library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$arith.all;

use ieee.std$\_$logic$\_$unsigned.all;

use ieee.numeric$\_$std$.$all;

entity Ram$\_8$Register$\_$Sarah$\_$John is

port $($

D: in std$\_$logic$\_$vector$(15$ downto $0)$;

Clock, load: in std$\_$logic;

address: in std$\_$logic$\_$vector$(2$ downto $0)$;

Q: out std$\_$logic$\_$vector$(15$ downto $0)$

$)$;

end Ram$\_8$Register$\_$Sarah$\_$John;

architecture behavioral of Ram$\_8$Register$\_$Sarah$\_$John is

type Array$8*16$ is array$(7$ downto $0)$ of std$\_$logic$\_$vector$(15$ downto $0)$;

signal RAM: Array$8*16$;

signal index: integer range $0$ to $7$;

begin

process $($Clock$)$

begin

if $($rising$\_$edge$($Clock$))$ then

if $($Load $=\text{'}1\text{'})$ then

for i in $0$ to $7$ loop

if address $=$ std$\_$logic$\_$vector$($to$\_$unsigned$($i$,3))$ then

RAM$($i D;

end if;

end loop;

end if;

for i in $0$ to $7$ loop

if address $=$ std$\_$logic$\_$vector$($to$\_$unsigned$($i$,3))$ then

Q RAM$($i$)$;

end if;

end loop;

end if;

end process;

end behavioral;