I need a test bench for this cood

I need a test bench for this cood 4 bit adder and subtractor cood Module name i have given it as jdoodle you can change it to whatever name according to your need module jdoodle (A, B, Cin, Sum, Cout); input A, B; input Cin; output Sum; output Cout; wire 11, 12, 13, 14; xor x1(t1,A,B): xor x2(Sum, t1,Cin); and 91(t2,A,B); and g2(13,B,Cin); and g3(14,Cin, A): or 94 (Cout,12,13,14); endmodule module add_sub_4 (A, B, In, Res, Out); input (3:0) A, B; input In; output (3:0) Res; output Out; wire 11,12,13,14,15,16,17; Kor 3(t3,B[0],in); xor x4(14,8[1],in); xor x5(t5,8[2].In); xor X6(t6,B[3].In); doodle f5(A[0],t3, In, Res[0],t1); doodle f6(A[1,14,In, Res[1],12): doodle f7(A[2],t5, In, Res[2],t3); doodle f8(A[3), t6, In, Res[3],Out); endmodule Screenshot for the above verilog code: + module fdoodle (A, B, C, Sun, Cout); 2 Enout A, B; 3input Cin 4 output Sun 5 outout Couts 6 dre ti, t2,3,4 7 xor xita, A.); 6 xor x2(Sun,ti.cin); 9 and gi(t2,4,5); 102(3,.cin); 11 and 3(te, Cin,A); 12 or (Cout,t2, 3, 4); 13 encodule 14 15 16 module ads_sub_4 (A, B, Is, Res, Out); 17Snput [3:03 A, 8 18 Snout In 19 output (3:0) Rest 2e output Out 21 wre t1, 12, 13, 14, 45, 46,47 22 23 24 xor 3(t3,8(e).In); 25 xor 44,01], In); 26 xor $(t5, [2, ); 27 xor (t6,B[3], In); 25 doodle (AO).t3, In, Resta) 29 doodle (A).t4.t1.Res. 2) se doodle 7 (A121.5.t2, Res[2.3) 31fdoodle FBCA[3).t6,t3, Res[33.0); 32 endodole