Question: I need help converting this Verilog code to VHDL module music(clk, speaker); input clk; output speaker; // first create a 16bit binary counter reg [15:0]

I need help converting this Verilog code to VHDL

module music(clk, speaker); input clk; output speaker; // first create a 16bit binary counter reg [15:0] counter; always @(posedge clk) counter <= counter+1; // and use the most significant bit (MSB) of the counter to drive the speaker assign speaker = counter[15]; endmodule

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