I need the testbench for the following code in VHDL quartus prime intel.

library ieee; use ieee.std_logic_1164.a11; use ieee. numeric_std. a 17; antity projectITCE is port c lk:in std_ logic; shift_char_in:in std_logic; reset:in std_logic; char:out std_7ogic_vector ( 1 downto 0); para11e1_out: out std_logic_vector (7 downto 0) end projectITCE; architecture rtl of projectITCE is type my_array is array(0 to 7) of std_7ogic_vector (1 downto 0); signal array_i: my_array :=(others ( others =>0) ); begin brocess (clk,shift_char_in) begin if rising_edge (clk) then if shift_char_in=" " then for i in 1 to 3 7oop array_i (i)