Imagine you are designing a pipelined processor for a new computing architecture. The processor has a $5-$stage pipeline $($Instruction Fetch, Instruction Decode, Execute, Memory Access, and Write Back$).$ During the testing phase, you observe that the pipeline is experiencing stalls and reduced throughput.

i$)$ Identify and explain at least two potential sources of stalls or performance bottlenecks in the pipeline.

ii$)$ Propose strategies or design enhancements to mitigate the identified issues and improve overall pipeline efficiency.

iii$)$ Discuss the trade$-$offs involved in implementing these strategies, considering factors such as complexity, cost, and impact on overall processor performance.